Many applications in industry can benefit from Ethernet and TCP/IP as it is a well-known and supported networking standard. More and more, these industrial applications require higher bandwidth and lower latency. This means that it is becoming a challenge not to overload the CPU with a TCP/IP stack running at maximum bandwidth. These increasing requirements make the processor spend more time handling data rather than running your application.

Easics' TCP/IP core can be used to offload the TCP/IP stack from the CPU and handle it in FPGA or ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible. The IP block is completely self-sufficient and can be used as a black box module which takes care of all networking tasks. This means that the rest of the system is free to use its processing power purely for application logic. In some use cases, integrating our full-hardware TCP/IP stack eliminates the need for any built-in embedded processor at all.

The Easics TCP/IP core is available as a 1 Gbit/s or 10 Gbit/s version. Both versions support Ethernet packets, IP packets, ICMP packets for ping, TCP packets and ARP packets. The 10 Gbit/s version additionally supports pause frames.


Application Areas

Some of the main application areas are listed below. Don't hesitate to contact us for feasibility advice of your use case.

  • networking in an industrial environment, for real-time automation and process control ('Industrial Ethernet' e.g. EtherCAT, PROFINET, POWERLINK, Modbus TCP, ...)
  • machine vision / multi-camera monitoring (e.g. GigE Vision)
  • test & measurement connectivity
  • networked storage, such as iSCSI
  • electronic trading, using Financial Information eXchange (FIX) protocol
  • ...


    Block Diagram




    The figure above shows the core’s building blocks and its four most important interfaces:

    • (X)GMII
    • user application FIFOs
    • memory interface
    • configuration interface

    The first of these is an industry-standard (X)GMII interface which communicates with a 1(0) Gbit PHY. The second is situated on the application side: two FIFOs with a simple push/pop interface, one for RX and one for TX. These FIFO interfaces, as well as an internal TCP block, communicate with a memory system which is to be provided outside of the core (the third interface). The size and type of memory can be selected by the user. ARM’s AMBA AXI4 2.0E is the protocol used for this communication. Various FPGA vendors, such as e.g. Xilinx, provide building blocks to interface internal block RAM, SRAM, or DRAM with an AXI bus. The fourth and final interface is used to configure various networking parameters and to read status info.


    Key Features
    • Ethernet Jumbo Frame up to 9000 bytes supported
    • Transmit and Receive buffers can be controlled to optimize the FPGA resource usage: 4kB up to 4GB per connection, internal SRAM or external memory.
    • Guaranteed in-order reception of all data at the application side (FIFO interfaces)
    • Fast response times to network traffic
    • Configurable MAC / IP address / TCP port
    • ARP server for mapping IP address onto MAC addresses. No need to manually set the ARP table in the PC.
    • ICMP echo protocol a.k.a. ping. This can be used for connectivity tests.
    • 1 active server connection per TCP port
    • Listens on fixed TCP port number, selectable at startup
    • TCP ACK piggybacking for reduced network load
    • Packet retransmit, both fast retransmit and timeout retransmit, with exponential back-off
    • Flow control, allowing backpressure from both server and client without data loss.
    • TCP Keep alive support (RFC1122)
    • TCP Zero window probes
    • TCP timestamps
    • Nagle algorithm (to prevent Silly Window Syndrome)
    • Round trip time measurement (RFC6298)
    • Congestion Avoidance: slow start and congestion window
    • Reordering for out-of-order packets
    • PAWS (protection against wrapped sequence numbers)
    • Very high throughput: > 99% of the theoretical 10 Gbit/s limit

    Refer to the Easics' TCP/IP core product brief for an extensive list of all features.


    Examples of Typical Use Cases


    Standalone Easics' TCP/IP core with 1 port



    Standalone Easics' TCP/IP core with 2 ports

    One TCP port is used to send and receive streaming data, while a second TCP port is used to control your hardware application.



    Easics' TCP/IP core as TOE

    Although an embedded microprocessor is not required, the Easics TCP/IP core can be used as a complete TCP/IP Offload Engine (TOE).



    Easics' TCP/IP core & microprocessor sharing an Ethernet connection

    The use case illustrated below shows another way of integrating both the Easics TCP/IP core and a microprocessor. The TCP mux routes Ethernet packets based on the TCP port number. The Ethernet traffic to 1 specific TCP port is routed to the Easics TCP/IP core. All other traffic is routed to the microprocessor. This approach offers a limited number of high-speed connections, processed by the Easics TCP/IP core and an unlimited number of lower speed connections, processed by the microprocessor.